Clocked comparators are used in systems that need to compare analog signals at specific times. Many such systems exist, including analog-to-digital converters, digital memories, disk drives, phase detectors for phase-locked loops, and receivers for serial communication systems. Clocked comparators are most often implemented as part of an integrated circuit fabricated in a semiconductor material. Their clocked operation enables reducing power while attaining high speed. However, many systems require increasingly high speeds where conventional designs reach their limit.
FIG. 1 illustrates a conventional clocked comparator 100 and its phases (table 199). It comprises a sense amplifier 110 and a set/reset (SR) latch 120 acting as a data storage element. Sense amplifier 110 may include an input stage 112, configured for comparing the levels of two analog data signals at its data inputs IN1 (130) and IN2 (132). It may further include an output stage 114 configured to amplify the comparison result to levels that SR latch 120 may interpret as digital data. Output signal AOUT1 is provided at node 140 and output signal AOUT2 is provided at node 142.
Clock input CLK 134 allows distinguishing two phases in the comparison process as illustrated in table 199. For instance, a first phase could be “precharge” and a second phase could be “evaluate”. Three states are possible at the two outputs of sense amplifier 110: [1] both AOUT1 and AOUT2 de-asserted: no measurement; [2] AOUT1 asserted and AOUT2 de-asserted: IN1>IN2; and [3] AOUT1 de-asserted and AOUT2 asserted: IN1<IN2. A fourth state where both outputs would be asserted is undefined. Asserted (active) may be defined as high or low, where de-asserted (inactive) is defined as the opposite.
For the SR latch 120, the “precharge” phase translates as a “hold” phase, in which its inputs “Set” and “Reset” are de-asserted. The output signals of sense amplifier 110 are coupled to “Set” and “Reset” inputs of SR latch 120. When SR latch 120 receives a “Set” signal at node 140, it will assert its output signal on output OUT (node 150), indicating that the result of a comparison is that the level of the IN1 signal is higher than the level of the IN2 signal. When it receives a “Reset” signal at node 142, it will de-assert its output signal on output OUT (node 150), indicating that the result of a comparison is that the level of the IN2 signal is higher than the level of the IN1 signal. SR latch 120 will hold its output stage until a new signal “Set” or “Reset” changes it.
The polarity of active signals of sense amplifier 110 and SR latch 120 needs to match. For instance if SR latch 120 has inactive signals high and active signals low, then the “Set” signal 140 is asserted when it is low and de-asserted when it is high. Similarly, the “Reset” signal 142 is asserted when it is low and de-asserted when it is high. Therefore, in that case sense amplifier 110 needs to output high signals while in the “hold” phase, and in an “evaluate” phase it should assert one of its outputs 140 or 142 by pulling it low. A similar reasoning, with opposite signal polarities, holds when inactive signals are low and active signals are high.
FIG. 2 illustrates a conventional sense amplifier 200 for a clocked comparator. It has analog inputs IN1 and IN2 at nodes 252 and 254, a clock input at node 250, outputs AOUT1 at node 256 and AOUT2 at node 258. It has a power supply rail VDD at node 230 and a ground rail GND at node 240. The circuit comprises three additional nodes: node 260 coupling a source terminal of M5 (205) with a drain terminal of M1 (201); node 262 coupling a source terminal of M6 (206) with a drain terminal of M2 (202); and node 264 coupling source terminals of M1 (201) and M2 (202) with a drain terminal of M7 (207).
Sense amplifier 200 has an input stage comprising transistors M1 (201) and M2 (202) configured as a differential pair and coupled with the input nodes 252 and 254. It includes an output stage comprising transistors M3-M6 (203-206) coupled with the input stage at nodes 260 and 262, and coupled with the output nodes 256 and 258. The output stage is configured as a differential amplifier with positive feedback.
In a first operational cycle (“precharge” or “hold” phase), when the signal at input CLK (node 250) is low (de-asserted), transistor M7 (207) is off and transistors M8 (208) and M9 (209) are on. There is no bias current flowing through transistors M1-M6 (201-206), and therefore the sense amplifier 200 is effectively in a sleep mode. The output signals AOUT1 and AOUT2 at nodes 256 and 258 are pulled high (de-asserted) by transistors M8 (208) and M9 (209), respectively.
At the start of a second operational cycle (“evaluate” phase), when a signal at input CLK (node 250) goes high, transistor M7 (207) starts conducting, while M8 (208) and M9 (209) stop conducting. Transistor M7 (207) provides a bias current for the sense amplifier 200, running through transistor M1 (201) and/or M2 (202). Transistors M1 (201) and M2 (202) of the input stage compare two analog input signals, applied at the IN1 and IN2 inputs respectively (nodes 252 and 254). If the signal at IN1 (node 252) is higher than the signal at IN2 (node 254), then M1 (201) conducts more than M2 (202), and vice-verse. The transistor with the highest conductance carries more current, and pulls its output node (260 or 262) to a lower voltage than the output node of the other transistor.
The output stage M3-M6 (203-206) is bistable because of the positive feedback, and therefore a small differential signal applied at its inputs (nodes 260 and 262) quickly results in one output reaching a voltage close to VDD and the other output reaching a voltage close to GND. Once this occurs, either transistor M1 (201) or transistor M2 (202) is deprived of current, ending the comparison. The sense amplifier 200 remains in the same state for the remainder of the “evaluate” phase. One of the outputs AOUT1 and AOUT2 is asserted, and the other is de-asserted.
Despite the potentially fast output stage, some non-idealities limit the circuit's performance.
Firstly, output stage M3-M6 (203-206) would be at its fastest in its linear region, where its inputs 260 and 262 and its outputs 256 and 258 are near half the supply voltage VDD. However, at the end of the “precharge” phase, these nodes 256-262 are all near VDD and positive feedback is interrupted because neither M3 (203) nor M4 (204) conducts. The output stage M3-M6 (103-106) is essentially in sleep mode and needs to wake up first.
Secondly, the transistors M1-M2 (201-202), M5-M6 (205-206), and M8-M9 (208-209) are not ideal conductors, and in modern semiconductor fabrication processes they cannot be expected to match very well. The nodes 256-264 all have some parasitic capacitance to ground. During the “precharge” phase, nodes 256-264 are all coupled with VDD (230) through differently conductive paths. As a result, the parasitic node capacitances will charge toward VDD at different rates, and there will be some offset between nodes 256 and 258, and between nodes 260 and 262. Offsets of the parasitic node capacitances, or of the drive strengths of transistors M1 (201) and M2 (202), may force the output stage M3-M6 (203-206) in the wrong direction, resulting in inaccurate response.
Thirdly, because at the end of the “evaluate” phase one output (256 or 258) is high and the other is low, during the subsequent “hold” or “precharge” phase the nodes on one side of the positive feedback amplifier M3-M6 (203-206) will substantially lag the nodes on the other side while their parasitic capacitances are charging toward VDD. Therefore, the offset between nodes 256-258 and the offset between nodes 260-262 will feature a memory effect which may still be present at the start of the “evaluate” phase that follows. As a result, when a change occurs in the comparison between the input signals 252 and 254, the change will require a sufficient input voltage to overcome the memory effect (or stored charge) to put the comparator in the other state because the offsets are forcing the positive feedback amplifier M3-M6 (203-206) in the wrong direction. The circuit effectively features hysteresis.
Because of these combined effects, the “evaluate” phase has an initially slow response, and a conventional clocked comparator may not be usable for applications that require the highest performance (speed) and accuracy.